View DG534A_7457452.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DG534A/538a vishay siliconix document number: 70069 s-00399?rev. e, 13-sep-99 www.vishay.com 1 4-/8-channel wideband video multiplexers

wide bandwidth: 500 mhz very low crosstalk: ?97 db @ 5 mhz on-board ttl-compatible latches with readback optional negative supply low r ds(on) : 45 single-ended or differential operation latch-up proof improved system bandwidth improved channel off-isolation simplified logic interfacing high-speed readback allows bipolar signal swings reduced insertion loss allows differential signal switching wideband signal routing and multiplexing video switchers ate systems infrared imaging ultrasound imaging

the DG534A is a digitally selectable 4-channel or dual 2-channel multiplexer. the dg538a is an 8-channel or dual 4-channel multiplexer. on-chip ttl-compatible address decoding logic and latches with data readback are included to simplify the interface to a microprocessor data bus. the low on-resistance and low capacitance of the these devices make them ideal for wideband data multiplexing and video and audio signal routing in channel selectors and crosspoint arrays. an optional negative supply pin allows the handling of bipolar signals without dc biasing. the DG534A/dg538a are built on a d/cmos process that combines n-channel dmos switching fets with low-power cmos control logic, drivers and latches. the low-capacitance dmos fets are connected in a ?t? configuration to achieve extremely high levels of off isolation. crosstalk is reduced to ?97 db at 5 mhz by including a ground line between adjacent signal paths. an epitaxial layer prevents latch-up. for more information refer to vishay siliconix applications note an502 (faxback document number 70609).

1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 gnd nc d a d b v+ v? s a1 s b1 gnd gnd s a2 s b2 4 /2 v l rs i /o dual-in-line top view 912 wr en 10 11 a 1 a 0 latches/drivers plcc 14 15 16 17 18 8 7 6 5 4 1 2 319 20 11 10 913 12 top view s a1 s b1 gnd gnd s a2 s b2 4 /2 v l rs nc 1 2 en i/o v+ d gnd d v? latch/drivers a a a b wr DG534Adn DG534Adj
DG534A/538a vishay siliconix www.vishay.com 2 document number: 70069 s-00399 ? rev. e, 13-sep-99

latch/drivers 1 2 3 4 5 6 7 8 28 27 26 25 24 23 22 21 top view gnd d b d a v ? v+ s b1 s a1 gnd gnd s b2 s a2 gnd gnd s b3 s a3 gnd 920 gnd s b4 dual-in-line 10 19 s a4 v l 11 12 18 17 8/4 rs en 13 16 wr a 0 14 15 a 2 a 1 i /o s a1 s b1 d d a b rs 0 a 1 2 i/o a a wr latch/drivers plcc 7 8 9 5 20 19 21 22 23 24 25 1 2 3 4 10 11 12 13 14 15 16 17 18 26 27 28 top view 6 gnd gnd s a2 s b2 gnd gnd s a3 s b3 gnd gnd s a4 s b4 8 /4 v l v+ gnd v ? en dg538adj dg538adn i /o a 1 a 0 en wr rs 4 /2 a on switch x x x x 1 1 maintains previous state x x x x x 0 x none (latches cleared) x x x 0 0 1 x none 0 0 0 1 0 1 0 s a1 0 0 1 1 0 1 0 s a2 d a and d b may be 0 1 0 1 0 1 0 s b1 d a and d b may be connected externally latches transparent 0 1 1 1 0 1 0 s b2 0 x 0 1 0 1 1 s a1 and s b1 0 x 1 1 0 1 1 s a2 and s b2 1 note b 1 1 note c logic ? 0 ? = v al 0.8 v logic ? 1 ? = v ah 2.4 v x = don ? t care
DG534A/538a vishay siliconix document number: 70069 s-00399 ? rev. e, 13-sep-99 www.vishay.com 3 i /o a 2 a 1 a 0 en wr rs 8 /4 a on switch x x x x x 1 1 maintains previous state x x x x x x 0 x none (latches cleared) x x x x 0 0 1 x none 0 0 0 0 1 0 1 0 s a1 0 0 0 1 1 0 1 0 s a2 0 0 1 0 1 0 1 0 s a3 0 0 1 1 1 0 1 0 s a4 d a and d b should be 0 1 0 0 1 0 1 0 s b1 d a and d b should be connected externally 0 1 0 1 1 0 1 0 s b2 latches transparent 0 1 1 0 1 0 1 0 s b3 0 1 1 1 1 0 1 0 s b4 0 x 0 0 1 0 1 1 s a1 and s b1 0 x 0 1 1 0 1 1 s a2 and s b2 0 x 1 0 1 0 1 1 s a3 and s b3 0 x 1 1 1 0 1 1 s a4 and s b4 1 note b 1 1 note c logic ? 0 ? = v al 0.8 v logic ? 1 ? = v ah 2 v x = don ? t care notes: a. connect d a and d b together externally for single-ended operation. b. with i /o high, a n and en pins become outputs and reflect latch contents. see timing diagrams for more detail. c. 8 /4 can be either ? 1 ? or ? 0 ? but should not change during these operations.

temperature range package part number DG534A 20-pin plastic dip DG534Adj ? 40 to 85 c 20-pin plcc DG534Adn ? 55 to 125 c 20-pin sidebraze DG534Aap/883, 5962-906021mrc dg538a 28-pin plastic dip dg538adj ? 40 to 85 c 28-pin plcc dg538adn ? 55 to 125 c 28-pin sidebraze dg538aap/883, 5962-8976001mxa
DG534A/538a vishay siliconix www.vishay.com 4 document number: 70069 s-00399 ? rev. e, 13-sep-99

v+ to gnd ? 0.3 v to +21 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v+ to v ?? 0.3 v to +21 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ? to gnd ? 10 v to +0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v l 0 v to (v+) + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital inputs (v ? ) ? 0.3 v to (v l ) + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or 20 ma, whichever occurs first v s , v d (v ? ) ? 0.3 v to (v ? ) + 14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or 20 ma, whichever occurs first current (any terminal) continuous 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . current(s or d) pulsed l ms 10% duty 40 ma . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature (a suffix) ? 65 to 150 c . . . . . . . . . . . . . . . . . . . (d suffix) ? 65 to 125 c . . . . . . . . . . . . . . . . . . . power dissipation (package) a plastic dip b 625 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . plcc c 450 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sidebraze d 1200 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: a. all leads soldered or welded to pc board. b. derate 8.3 mw/ c above 75 c. c. derate 6 mw/ c above 75 c. d. derate 16 mw/ c above 75 c.

test conditions unless otherwise specified a suffix ? 55 to 125 c d suffix ? 40 to 85 c parameter symbol v+ = 15 v, v ? = ? 3 v, v l = 5 v wr = 0.8 v, rs , en= 2 v temp b typ c min d max d min d max d unit analog switch analog signal range g v analog v ? = ? 5 v full ? 5 8 ? 5 8 v drain-source on-resistance r ds(on) i s = ? 10 ma, v s = 0 v room full 45 90 120 90 120 r ds(on) v ail = 0.8 v, v aih = 2 v sequence each switch on room 9 9 source off leakage current i s(off) v s = 8 v, v d = 0 v, en = 0.8 v room full 0.05 ? 5 ? 50 5 50 ? 5 ? 50 5 50 drain off leakage current i d(off) v s = 0 v, v d = 8 v, en = 0.8 v room full 0.1 ? 20 ? 500 20 500 ? 20 ? 100 20 100 na drain on leakage current i d(on) v s = v d = 8 v room full 0.1 ? 20 ? 1000 20 1000 ? 20 ? 200 20 200 digital control input voltage high v aih full 2 2 input voltage low v ail full 0.8 0.8 v address input current i ai v ai = 0 v, or 2 v or 5 v room full ? 0.1 ? 1 ? 10 1 10 ? 1 ? 10 1 10 a v ao = 2.7 v room ? 21 ? 2.5 ? 2.5 address output current i ao v ao = 0.4 v room 3.5 2.5 2.5 ma dynamic characteristics on state input plcc room 28 40 40 on state input capacitance g c s(on) see figure 11 dip room 31 45 45 off state input plcc room 3 5 4 off state input capacitance g c s(off) dip room 4 5 pf off state output see figure 12 plcc room 6 10 8 off state output capacitance g c d(off) dip room 8 10 transition time t trans room full 160 300 500 300 500 break-before-make interval t open see figure 4 room full 80 50 25 50 25 en, wr turn on time t on see figure 2 and 3 room full 150 300 500 300 500 ns en, turn off time t off see figure 2 room full 105 175 300 175 300 charge injection qi see figure 5 room ? 70 pc
DG534A/538a vishay siliconix document number: 70069 s-00399 ? rev. e, 13-sep-99 www.vishay.com 5

test conditions unless otherwise specified a suffix ? 55 to 125 c d suffix ? 40 to 85 c parameter symbol v+ = 15 v, v ? = ? 3 v, v l = 5 v wr = 0.8 v, rs , en= 2 v temp b typ c min d max d min d max d unit dynamic characteristics (cont?d) r l = 75 f = 5 mhz plcc room ? 75 chip disabled crosstalk f x talk(cd) en = 0.8 v see figure 8 dip room ? 65 r in = 10 r l = 10 k plcc room ? 97 adjacent input crosstalk f x talk(ai) r l = 10 k ? 87 adjacent input crosstalk x talk(ai) r in = 75 , r l = 75 plcc room ? 80 f = 5 mhz see figure 7 dip room ? 70 r in = 10 r l = 10 k plcc room ? 77 db all hostile crosstalk x talk(ah) r l = 10 k ? 72 all hostile crosstalk x talk(ah) r in = 75 , r l = 75 plcc room ? 77 f = 5 mhz see figure 7 dip room ? 72 r in = 10 , r l = 10 k f = 5 mhz, see figure 10 room ? 84 differential crosstalk x talk(diff) r in = r l = 75 f = 5 mhz, see figure 10 room ? 84 bandwidth bw r l = 50 , see figure 6 room 500 mhz power supplies positive supply current i+ any one channel selected with ad- room full 0.6 2 5 2 5 negative supply current i ? any one channel selected with ad- dress inputs at gnd or 5 v room full 0.6 ? 1.8 ? 2 ? 1.8 ? 2 ma v+ to v ? full 10 21 10 21 functional check of maximum operating v ? to gnd functional test only full ? 5.5 0 ? 5.5 0 v supply voltage range v+ to gnd full 10 21 10 21 logic supply current i l full 150 500 500 a timing reset to write t rw room full ? 22 50 50 wr , rs minimum pulse width t mpw room full 60 200 200 a 0 , a 1 , en data valid to strobe t dw room full 20 100 100 a 0 , a 1 , en data valid after strobe t wd see figure 1 room full ? 20 50 50 ns address bus tri-state e t az room 25 address bus output t ao room 95 address bus input t ai room 110 notes: a. refer to process option flowchart. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data s heet. e. defined by system bus requirements. f. each individual pin shown as gnd must be grounded. g. guaranteed by design, not subject to production test.
DG534A/538a vishay siliconix www.vishay.com 6 document number: 70069 s-00399 ? rev. e, 13-sep-99

d a d b decode en v ? en s a1 s a2 s b1 s b2 s a3 s a4 s b3 s b4 wr a 2 a 1 a 0 v l rs 8 /4 v ref v ref v ref v ref v ref v ref v ref v ref i /o a 2 a 1 a 0 a 2 a 1 a 0 s a1 ? s a4 s b1 ? s b4 d a , d b latch i /o decode tri-state buffer v ? v ? v ? v+ v ? v l ** *typical all readback (a x , en) pins v l
DG534A/538a vishay siliconix document number: 70069 s-00399 ? rev. e, 13-sep-99 www.vishay.com 7

supply currents vs. temperature leakage vs. temperature r ds(on) vs. v d and temperature adjacent input crosstalk vs. frequency address, en output current vs. temperature r ds(on) vs. v ? , v+ current (ma) current (ma) leakage r ds(on) ? drain-source on-resistance ( ) (db) talk(ai) x temperature ( c) temperature ( c) temperature ( c) v ? ? negative supply (v) v d ? drain voltage (v) f ? frequency (mhz) 1.4 1.0 0.6 ? 0.2 ? 0.6 ? 1.4 70 60 50 40 30 ? 6 ? 5 ? 4 ? 3 ? 2 ? 10 ? 40 ? 20 0 20 40 60 80 100 120 ? 40 ? 20 0 20 40 60 80 100 120 v+ = 15 v v ? = ? 3 v v l = 5 v i+ i s(off) i d(on) v+ = 10 v v+ = 12 v v+ = 15 v v d = 0 v v l = 5 v i s = ? 10 ma 8 0 ? 8 ? 16 ? 32 ? 40 ? 20 0 20 40 60 80 100 120 0.2 ? 1.0 v+ = 15 v v ? = ? 3 v v l = 5 v i ? ? 24 (source) i l 1 a 100 na 10 na 1 na 100 pa 10 pa 1 pa v ao = 0.4 v v ao = 2.7 v v+ = 15 v v ? = ? 3 v v l = 5 v 200 180 160 140 120 ? 20 24 6810 100 80 60 40 20 ? 100 ? 80 ? 60 ? 40 ? 20 1 10 100 v+ = 15 v v ? = ? 3 v v l = 5 v i s = ? 10 ma v+ = 15 v v ? = ? 3 v v l = 5 v r in = 10 r l = 10 k 125 c ? 55 c plcc dip i d(off) 25 c (sink) r ds(on) ? drain-source on-resistance ( )
DG534A/538a vishay siliconix www.vishay.com 8 document number: 70069 s-00399 ? rev. e, 13-sep-99

adjacent input crosstalk vs. frequency adjacent input crosstalk vs. frequency differential crosstalk vs. frequency differential crosstalk vs. frequency all hostile crosstalk vs. frequency all hostile crosstalk vs. frequency (db) talk(ai) x (db) talk(ai) x (db) talk(ah) x (db) talk(ah) x f ? frequency (mhz) f ? frequency (mhz) f ? frequency (mhz) f ? frequency (mhz) f ? frequency (mhz) f ? frequency (mhz) ? 100 ? 80 ? 60 ? 40 ? 20 1 10 100 plcc dip v+ = 15 v v ? = ? 3 v v l = 5 v r in = r l = 75 ? 100 ? 80 ? 60 ? 40 ? 20 1 10 100 plcc dip v+ = 15 v v ? = ? 3 v v l = 5 v r in = 10 r l = 10 k ? 100 ? 80 ? 60 ? 40 ? 20 1 10 100 ? 100 ? 80 ? 60 ? 40 ? 20 1 10 100 plcc dip v+ = 15 v v ? = ? 3 v v l = 5 v r in = 10 r l = 10 k plcc dip v+ = 15 v v ? = ? 3 v v l = 5 v r in = r l = 75 ? 100 ? 80 ? 60 ? 40 ? 20 1 10 100 plcc dip v+ = 15 v v ? = ? 3 v v l = 5 v r in = 10 r l = 10 k ? 100 ? 80 ? 60 ? 40 ? 20 1 10 100 plcc dip v+ = 15 v v ? = ? 3 v v l = 5 v r in = 75 r l = 75 (db) talk(diff) x (db) talk(diff) x
DG534A/538a vishay siliconix document number: 70069 s-00399 ? rev. e, 13-sep-99 www.vishay.com 9

switching times vs. temperature transition time vs. temperature time (ns) time (ns) temperature ( c) temperature ( c) 225 ? 40 40 120 250 ? 20 0 20 60 80 100 200 175 150 125 100 75 t trans 225 ? 40 40 120 50 ? 20 0 20 60 80 100 t bbm t off t on 200 175 150 125 100 75

figure 1. don ? t care write data don ? t care don ? t care new data don ? t care driven bus hi z device data* out hi z driven bus writing data to device delay time required after reset before write 3 v 0 v 3 v 0 v 3 v 0 v 3 v 0 v 3 v 0 v 3 v 0 v 3 v 0 v 3 v 0 v reading data from device wr rs a 0 , a 1 , a 2 , en i /o wr wr t wd t mpw t az t ai t ao a 0 , a 1 , a 2 , en a 0 , a 1 , a 2 , en t mpw t dw t rw
DG534A/538a vishay siliconix www.vishay.com 10 document number: 70069 s-00399 ? rev. e, 13-sep-99

figure 2. en, cs, cs , turn on/off time figure 3. wr , turn on time v l a 0 a 1 , a 2 +15 v en v+ v ? gnd v o s bn s a1 ? s bn-1 8 /4, 4 /2 1 k +1 v +5 v + 10 f 100 nf rs i /o + 10 f 100 nf ? 3 v wr 45 pf d a d b logic input t r <20 ns t f <20 ns en v out t off t on switch output 3 v 0 v 50% 90% v ? ? 3 v v o 1 k s a1 s a2 ? s bn 8 /4, 4 /2 +1 v 45 pf d a d b en, v l , rs a 0 + a 1 , a 2 10 f 100 nf i /o wr + logic input t r <20 ns t f <20 ns 10 f 100 nf address logic logic input +15 v v+ gnd +5 v +3 v 0 v wr v out t on (wr ) a 0 +3 v 0 v 90% 0 v
DG534A/538a vishay siliconix document number: 70069 s-00399 ? rev. e, 13-sep-99 www.vishay.com 11

figure 4. transition time and break-before-make interval figure 5. charge injection transition time (t trans ) v out s 1 s 16 turning off turning on bbm interval a 0 , a 1 , a 2 50% 90% 3 v 0 v v o s b1 1 k s a1 en s a2 ? s bn 8 /4 or 4 /2 45 pf d a d b v l a 0 , a 1 , a 2 + 10 f 100 nf rs i /o wr logic input t r <20 ns t f <20 ns + 10 f 100 nf logic input v ? ? 3 v +15 v v+ gnd +5 v +1 v en v out v out v out is the measured voltage error due to charge injection. the charge injection in cou- lombs is q = c l x v out en 8 /4 or 4 /2 v o v+ d a d b i /o wr s bn a 0 , a 1 , a 2 , rs + 10 f + 100 nf 10 f 100 nf c l = 1000 pf gnd v ? ? 3 v +15 v v l +5 v
DG534A/538a vishay siliconix www.vishay.com 12 document number: 70069 s-00399 ? rev. e, 13-sep-99

figure 6. bandwidth figure 7. all hostile crosstalk figure 8. chip disabled crosstalk v o d a s a2 ? s bn a 0 to a 2 v l + 10 f + 100 nf 10 f 100 nf rs i /o wr en 8 /4, 4 /2 v in s a1 50 v ? ? 3 v +15 v v+ gnd +5 v note: s a1 on or any other one channel on. all channels off 8 /4 or 4 /2 = logic ? 0 ? r l 75 r l v out d a d b s a1 r in s an s b1 s bn v out d a d b s a1 s an s b1 s bn figure 9. adjacent input crosstalk figure 10. differential crosstalk channels s a1 and s b1 on 4 /2 = logic ? 1 ? signal generator r l v out d a d b s a1 r in s an s b1 s bn r in 10 r l 10 k r in 10 w s n s n+1 v sn ? 1 v sn v sn+1 s n ? 1 x talk(ai) 20 log 10 v sn ? 1 v sn or 20 log 10 v sn 1 v sn v r l x talk(ah) 20 log 10 v out v x talk(cd) 20 log 10 v out v x talk(diff) 20 log 10 v out v
DG534A/538a vishay siliconix document number: 70069 s-00399 ? rev. e, 13-sep-99 www.vishay.com 13

meter hp4192a impedance analyzer or equivalent figure 11. on state input capacitance figure 12. off state input/output capacitance s b1 s a1 en 8 /4 or 4 /2 d a d b v l rs i /o wr v ? ? 3 v v+ gnd +5 v a 0 a 2 a 1 s an s bn +15 v s b1 s a1 en v l rs i /o wr v ? ? 3 v v+ gnd +5 v s a2 s b2 +15 v 8 /4 or 4 /2 d a d b meter hp4192a impedance analyzer or equivalent
! 22 21 20 19 18 17 16 15 14 13 12 11 10 ? 5 ? 4 ? 3 ? 2 ? 1 ? 5.5 0 notes: a. both v+ and v ? must have decoupling capacitors mounted as close as possible to the device pins. typical decoup- ling capacitors would be 10- f tantalum bead in parallel with 100-nf ceramic disc. b. production tested with v+ = 15 v and v ? = ? 3 v. a. for v l = 5 v 10%, 0.8- or 2-v ttl compatibility is maintained over the entire operating voltage range. allowable operating voltage area (note b) positive supply voltage v+ (volts) negative supply voltage v ? (volts) figure 13.
DG534A/538a vishay siliconix www.vishay.com 14 document number: 70069 s-00399 ? rev. e, 13-sep-99

pin number symbol DG534Adj dg538a description d a 2 2 analog output/input v+ 3 3 positive supply voltage s a1 4 4 analog input/output s a2 6 6 analog input/output s a3 ? 8 analog input/output s a4 ? 10 analog input/output 4 /2 7 ? 4 x 1 or 2 x 2 select 8 /4 ? 11 8 x 1 or 4 x 2 select rs 8 12 reset wr 9 13 write command that latches a, en a 0 , a 1 , a 2 11, 10, ? 16, 15, 14 binary address inputs that determine which channel(s) is/are connected to the out- put(s) en 12 17 enable. input/output, if en = 0, all channels are open i /o 13 18 input/output control. used to write to or read from the address latches v l 14 19 logic supply voltage, usually +5 v s b4 ? 20 analog input/output s b3 ? 22 analog input/output s b2 15 24 analog input/output s b1 17 26 analog input/output v ? 18 27 negative supply voltage d b 19 28 analog output/input gnd 1, 5, 16 1, 5, 7, 9, 21, 23, 25 analog and digital grounds. all grounds should be connected externally to optimize dynamic performance

device description the DG534A/538a d/cmos wideband multiplexers offer single-ended or differential functions. a 8 /4 or 4 /2 logic input pin selects the single-ended or differential mode. to meet the high dynamic performance demands of video, high definition tv, digital data routing (in excess of 100 mbps), etc., the DG534A/538a are fabricated with dmos transistors configured in ? t ? arrangements with second level ? l ? configurations (see functional block diagram). use of dmos technology yields devices with very low capacitance and low r ds(on) . this directly relates to improved high frequency signal handling and higher switching speeds, while maintaining low insertion loss figures. the ? t ? and ? l ? switch configurations further improve dynamic performance by greatly reducing crosstalk and output node capacitances. the DG534A/dg538a are improved pin-compatible replacements for the non-a versions. improvements include: higher current readback drivers, readback of the en bit, latchup protection frequency response a single multiplexer on-channel exhibits both resistance [r ds(on) ] and capacitance [c s(on) ]. this rc combination causes a frequency dependent attenuation of the analog signal. the ? 3-db bandwidth of the DG534A/538a is typically 500 mhz (into 50 ). this figure of 500 mhz illustrates that the switch-channel cannot be represented by a simple rc combination. the on capacitance of the channel is distributed along the on-resistance, and hence becomes a more complex multi-stage network of r ? s and c ? s making up the total r ds(on) and c s(on) .
DG534A/538a vishay siliconix document number: 70069 s-00399 ? rev. e, 13-sep-99 www.vishay.com 15

" power supplies and decoupling a useful feature of the DG534A/538a is its power supply flexibility. it can be operated from unipolar supplies (v ? connected to 0 v) if required. allowable operating voltage ranges are shown in figure 13. note that the analog signal must not go below v ? by more than 0.3 v (see absolute maximum ratings). however, the addition of a v ? pin has a number of advantages: a. it allows flexibility in analog signal handling, i.e. with v ? = ? 5 v and v+ = 15 v, up to 5 v ac signals can be accepted. b. the value of on capacitance (c s(on) ) may be reduced by increasing the reverse bias across the internal fet body to source junction. v+ has no effect on c s(on) . it is useful to note that tests indicate that optimum video differential phase and gain occur when v ? is ? 3 v. c. v ? eliminates the need to bias an ac analog signal using potential dividers and large decoupling capacitors. it is established rf design practice to incorporate sufficient bypass capacitors in the circuit to decouple the power supplies to all active devices in the circuit. the dynamic performance of the dg534/538 is adversely affected by poor decoupling of power supply pins. also, since the substrate of the device is connected to the negative supply, proper decoupling of this pin is essential. rules: a. decoupling capacitors should be incorporated on all power supply pins (v+, v ? , v l ). b. they should be mounted as close as possible to the device pins. c. capacitors should have good frequency characteristics - tantalum bead and/or ceramic disc types are suitable. recommended decoupling capacitors are 1- to 10- f tantalum bead, in parallel with 100-nf ceramic or polyester. d. additional high frequency protection may be provided by 51- carbon film resistors connected in series with the power supply pins (see figure 14). board layout pcb layout rules for good high frequency performance must also be observed to achieve the performance boasted by the DG534A/538a. some tips for minimizing stray effects are: a. use extensive ground planes on double sided pcb separating adjacent signal paths. multilayer pcb is even better. b. keep signal paths as short as practically possible with all channel paths of near equal length. c. use strip-line layout techniques. improvements in performance can be obtained by using plcc parts instead of dips. the stray effects of the quad plcc package are lower than those of the dual-in-line packages. sockets for the plcc packages usually increase crosstalk. DG534A +5 v +15 v ? 3 v + ++ v ? v+ gnd s a1 s a2 s b1 s b2 d a d b c 2 c 1 c 1 c 2 51 w 51 51 c 1 c 2 c 1 = 1 f tantalum c 2 = 100 nf polyester figure 14. DG534A power supply decoupling v l interfacing logic interfacing is easily accomplished. comprehensive addressing and control functions are incorporated in the design. the v l pin permits interface to various logic types. the device is primarily designed to be ttl or cmos logic compatible with +5 v applied to v l . the actual logic threshold can be raised simply by increasing v l .
DG534A/538a vishay siliconix www.vishay.com 16 document number: 70069 s-00399 ? rev. e, 13-sep-99

" a typical switching threshold versus v l is shown in figure 15. these devices feature an address readback (tally) facility, whereby the last address written to the device may be output to the system. this allows improved status monitoring and hand shaking without additional external components. this function is controlled by the i /o pin, which directly addresses the tri-state buffers connected to the en and address pins. en and address pins can be assigned to accept data (when i /o = 0; wr = 0; rs = 1), or output data (when i /o = 1; wr = 1; rs = 1), or to reflect a high impedance and latched state (when i /o = 0; wr = 1; rs = 1). when i /o is high, the address output can sink or source current. note that v l is the logic high output condition. this point must be respected if v l is varied for input logic threshold shifting. further control pins facilitate easy microprocessor interface. on chip address, data latches are activated by wr , which serves as a strobe type function eliminating the need for peripheral latch or memory i/o port devices. also, for ease of interface, a direct reset function (rs ) allows all latches to be cleared and switches opened. reset should be used during power up, etc., to avoid spurious switch action. see figure 16. channel address data can only be entered during wr low, when the address latches are transparent and i /o is low. similarly, address readback is only operational when wr and i /o are high. the siliconix clc410 video amplifier is recommended as an output buffer to reduce insertion loss and to drive coaxial cables. for low power video routing applications or for unity gain input buffers clc111/clc114 are recommended. 8 7 6 5 4 3 2 1 0 024681012141618 v th (v) v l (v) figure 15. switching threshold voltage vs. v l reset address decoder wr video bus data bus address bus data bus i /o 75 75 75 75 clc410 a v = 2 clc410 clc410 clc410 DG534A DG534A figure 16. DG534A in a video matrix wr en rs s a1 s b2 a 0 , a 1 d a d b en wr rs s a1 s b2 a 0 , a 1 d a d b

▲Up To Search▲

Price & Availability of DG534A

	To Download DG534A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .